EVAL-AD5443EB【PDF 14/24 页】CAP X7R 470PF 50V 10% 0603

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REV. 0

–14–

AD5426/AD5432/AD5443

Table III shows the relationship between digital code and the

expected output voltage for bipolar operation (AD5426, 8-bit

device).

Table III. Bipolar Code Table

Digital Input

Analog Output (V)

1111 1111

1000 0000

0000 0001

0000 0000

REF

(127/128)

–V

REF

(127/128)

–V

REF

(128/128)

Stability

In the I-to-V configuration, the I

OUT

of the DAC and the invert-

ing node of the op amp must be connected as close as possible,

and proper PCB layout techniques must be employed. Since

every code change corresponds to a step function, gain peaking

may occur if the op amp has limited GBP and there is excessive

parasitic capacitance at the inverting node. This parasitic capaci-

tance introduces a pole into the open-loop response which can

cause ringing or instability in closed-loop applications.

An optional compensation capacitor, C1 can be added in parallel with

for stability as shown in Figures 6 and 7. Too small a value of

C1 can produce ringing at the output, while too large a value can

adversely affect the settling time. C1 should be found empirically

but 1 pF to 2 pF is generally adequate for compensation.

SINGLE-SUPPLY APPLICATIONS

Current Mode Operation

These DACs are specified and tested to guarantee operation in

single-supply applications. Figure 8 shows a typical circuit for

operation with a single 3.0 V to 5 V supply. In the current mode

circuit of Figure 8, I

OUT

and hence I

OUT

1 is biased positive by

an amount applied to V

BIAS

OUT

GND

OUT

REF

BIAS

NOTES

1. ADDITIONAL PINS OMITTED FOR CLARITY

2. C1 PHASE COMPENSATION (1pF–2pF) MAY BE REQUIRED

IF A1 IS A HIGH SPEED AMPLIFIER.

Figure 8. Single-Supply Current Mode Operation

In this configuration, the output voltage is given by

(

OUT

DAC

BIAS

)

{

}

As D varies from 0 to 255 (AD5426), 1023 (AD5432) or 4095

(AD5443), the output voltage varies from

to V

OUT

BIAS

OUT

BIAS

should be a low impedance source capable of sinking and

sourcing all possible variations in current at the I

OUT

2 terminal

without any problems.

It is important to note that V

is limited to low voltages because

the switches in the DAC ladder no longer have the same source-

drain drive voltage. As a result, their on resistance differs, which

degrades the linearity of the DAC. See TPCs 10 to 15.

OUT

–V

REF

to +V

REF

SCLK SDIN

GND

REF

10V

SYNC

OUT

REF

NOTES

1. R1 AND R2 ARE USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.

ADJUST R1 FOR V

= 0 V WITH CODE 10000000 LOADED TO DAC.

2. MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS R3 AND R4.

3. C1 PHASE COMPENSATION (1pF–2pF) MAY BE REQUIRED IF A1/A2 IS

A HIGH SPEED AMPLIFIER.

AGND

10k

AD5426/

AD5432/AD5443

20k

10k

MICROCONTROLLER

Figure 7. Bipolar Operation

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